Timeline



Jul 20, 2017: Yesterday

12:39 AM Changeset in core/math/modexpa7 [c6ea5d8]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Force inference of distributed memory for the simple FIFO used to …
12:36 AM Changeset in core/math/modexpa7 [ce4b574]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Converted pe_c_out_mem two-dimensional array into a FIFO.

Jul 19, 2017:

6:49 PM Changeset in core/math/modexpa7 [c3d75e5]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Fixed bug in systolic multiplier (swapped indices), it only worked …
6:09 PM Changeset in core/math/modexpa7 [7486edd]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Added pre-multiplication step. Added 512-bit testbench.
12:00 PM Changeset in core/math/modexpa7 [344ed1b]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Finished modular exponentiation module: * works in simulator * …

Jul 17, 2017:

11:26 PM Changeset in core/math/modexpa7 [d887154]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Started adding exponentiator module w/ testbench.
11:14 PM Changeset in user/shatov/modexp_fpga_model [2db58a7]master by Pavel V. Shatov (Meister) <meisterpaul1@…>
Changes to the model: * Follow what Verilog does more closely: FPGA …

Jul 13, 2017:

6:38 PM Changeset in core/math/modexpa7 [72a67f0]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Systolic multiplier simplified a bit: * passes testbench tests again …

Jul 10, 2017:

12:31 PM Changeset in core/math/modexpa7 [71b7529]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
* made separate file for low-level settings * turned crazy triple …

Jul 8, 2017:

4:40 PM Changeset in user/shatov/modexp_fpga_model [9e56430] by Pavel V. Shatov (Meister) <meisterpaul1@…>
Minor update, there's no need to update Aj inside of systolic loop.

Jul 7, 2017:

10:22 PM Changeset in user/sra/openssl-engine [10ade41]master by Rob Austein <sra@…>
Cleanup.
3:02 AM GitRepositories/user/sra/openssl-engine edited by trac
(diff)
2:42 AM Changeset in user/sra/openssl-engine [3cb262f] by Rob Austein <sra@…>
TLS example.

Jul 5, 2017:

1:24 PM Changeset in user/shatov/modexp_fpga_model [ee41d58] by Pavel V. Shatov (Meister) <meisterpaul1@…>
Turned systolic multiplication into a separate routine.
1:04 PM Changeset in user/shatov/modexp_fpga_model [6e36e87] by Pavel V. Shatov (Meister) <meisterpaul1@…>
Triple multiplier turns out to be an overkill in Verilog, started …

Jul 4, 2017:

1:33 PM Changeset in core/math/modexpa7 [0da7120]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Fixed generic/vendor low-level primitives switch.
1:25 PM Changeset in core/math/modexpa7 [b3f9191]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Fixing generic/vendor primitive switching…

Jul 1, 2017:

7:26 PM Changeset in core/math/modexpa7 [caea5e3]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Started porting generic multiplier to Xilinx primitives.
5:11 PM Changeset in core/math/modexpa7 [a62861f]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Added generic/vendor-specific primitive selector for simulation.
4:38 PM Changeset in core/math/modexpa7 [73fd793]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Cleaned up Verilog sources
3:47 PM Changeset in core/math/modexpa7 [a69a530]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Added 512-bit test vector Cleaned up Verilog a bit

Jun 30, 2017:

11:05 PM Changeset in core/math/modexpa7 [1fd8037]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Finished modulus-dependent coefficient calculation module: * fixed …

Jun 28, 2017:

10:15 PM Changeset in user/shatov/modexp_fpga_model [e91ce07] by Pavel V. Shatov (Meister) <meisterpaul1@…>
Follow what Verilog does more precisely.

Jun 27, 2017:

5:04 PM GitRepositories edited by trac
(diff)
10:49 AM Changeset in core/math/modexpa7 [52675d5]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Added test vectors, use scripts from the C model to (re-)generate them.
10:48 AM Changeset in core/math/modexpa7 [e4b7015]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Added Montgomery modulus-dependent coefficient calculation block * …
10:47 AM Changeset in core/math/modexpa7 [6120612]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Added Montgomery factor calculation block * works in simulator * …
10:44 AM Changeset in core/math/modexpa7 [0b87350]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Added systolic modular multiplier w/ testbench. * works in simulator …
10:42 AM Changeset in core/math/modexpa7 [46b01cb]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Added generic processing elements.
10:39 AM Changeset in core/math/modexpa7 [970ae50]systolic by Pavel V. Shatov (Meister) <meisterpaul1@…>
Start conversion to systolic architecture.

Jun 24, 2017:

8:29 PM Changeset in user/shatov/modexp_fpga_model [22f6cc0] by Pavel V. Shatov (Meister) <meisterpaul1@…>
Improved the model: * added CRT support * fixed bug in systolic …
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